This invention relates generally to electronic countermeasures for protecting a target from adversary radar systems and radar guided weapons. This invention relates particularly to generating a false target radar image for countering wideband synthetic aperture and inverse synthetic aperture imaging radars.
Modern shipboard and airborne wideband synthetic aperture radars (SARs) and inverse synthetic aperture radars (ISARs) are capable of generating images of target objects. Such imaging capability is an advantage over previous technology because it improves the ability to identify the specific type of target, distinguish friend from foe, accurately guide weaponry, and defeat electronic protection such as false target decoys. Thus, modern wideband imaging SARs and ISARs create a difficult ship defense problem. For example, if an adversary is using a wideband imaging ISAR, an electronic protection system cannot synthesize a false target by just transmitting a signal that emulates a radar return off a single or a few scattering surfaces. Instead, such a transmitted signal must emulate a coherent sequence of reflections with the proper delay, phase, and amplitude that is similar to what would come from the multiple scattering surfaces at multiple ranges (distances from the radar) of an actual ship.
Analog methods for generating false radar targets have included the use of acoustic charge transport (ACT) tapped delay lines and fiber optic tapped delay lines. ACT devices are no longer commercially available and also have limited bandwidth, making them impractical against wideband imaging radars. Optical devices are bulky and costly to manufacture, especially for the longer delay line lengths needed to synthesize a false target image of even a moderately sized ship.
An object of the present invention provides a system and method for producing false target images for both small and large targets, even up to the size of an aircraft carrier.
Another object of the invention is to provide a false target image generation system that is fully programmable.
A system according to the present invention for generating a false target radar image for countering wideband synthetic aperture and inverse synthetic aperture imaging radar systems to prevent a selected target from being detected by such radar systems comprises a receiver system for producing a signal that represents an incident radar pulse. A phase sampling circuit is connected to the receiver for sampling the signal and providing phase sample data. An image synthesizer circuit is connected to the phase sampling circuit and arranged to receive the phase sample data therefrom. The digital image synthesizer circuit is arranged to process the phase sample data to form a false target signal, which is input to a signal transmitter system arranged to transmit the synthesized false target signal so that it can be received by a radar system.
The receiver system preferably comprises a down-converting radar receiver for producing an output in response to a received radar signal. An oscillator is connected to the down converter for providing a reference signal thereto. The down converter is arranged to process the reference signal and the wide-band chirp signal to produce a signal component I that is in phase and a component Q that is in quadrature with the wideband chirp signal. The phase sampling circuit preferably comprises a phase sampling digital radio frequency memory connected to the down converter to receive the signals I and Q therefrom. The image synthesizer circuit is arranged to calculate numerical values of in-phase and quadrature components of the false target signal.
The transmitter system preferably comprises a pair of digital to analog converters connected to the image synthesizer circuit and arranged to produce analog signal components corresponding to the false target in-phase and quadrature digital image signal components. An up converter is connected to the pair of digital to analog converters and to the local oscillator. The up converter is arranged to convert the analog signal components into a synthesized false target image signal that is input to a signal transmitter arranged to transmit the synthesized false target image signal so that it can be received by a radar system.
The image synthesizer circuit preferably comprises a linear array of range bin processors (RBPs) arrange to calculate numerical values for the false target in-phase and quadrature digital image signals. The range bin processors preferably operate under the control of a microprocessor. Each of the range bin processors preferably comprises a phase rotation adder having inputs connected to the microprocessor and to the phase sampling digital radio frequency memory. The phase rotation adder is arranged to add phase rotation data received from the microprocessor to phase samples received from the phase sampling digital radio frequency memory to produce a signal with a rotated phase angle. A read only memory is arranged to receive the phase rotation signal from the phase rotation adder and provide output signals that indicate the sine and cosine of the phase rotation angle. A first summation adder is arranged to add the sine signal to a partial Q summation of sine signals from the previous range bin in the linear array and produce a new partial Q summation that is input to the next range bin in the array. A second summation adder is arranged to add the cosine signal to a partial I summation of cosine signals from the previous range bin in the linear array and produce a new partial I summation that is input to the next range bin in the array.
The system according to the present invention preferably further comprises a phase rotation buffer connected to the microprocessor to receive the phase rotation data therefrom, and a phase rotation register connected between the phase rotation buffer and the phase rotation adder.
The system according to the present invention preferably also further comprises a gain buffer connected to the microprocessor to receive gain data therefrom and a gain register connected to the gain buffer. A first gain multiplier is arranged to receive the sine signal as a first input and a signal output from the gain register as a second input. The gain multiplier is further arranged to provide the sine signal to the summation adder. A second gain multiplier is arranged to receive the cosine signal as a first input and a signal output from the gain register as a second input. The gain multiplier is further arranged to provide the sine signal to the summation adder.